In the manufacture of semiconductor devices, ion implantation is often used to dope semiconductor workpieces (e.g., silicon wafers) with impurities. For example, ion implanters or ion implantation systems may treat a workpiece with an ion beam, to produce n-type or p-type doped regions or to form passivation layers on the workpiece. When used for doping semiconductors, the ion implantation system injects a selected ion species to produce the desired extrinsic material.
Since the size of a workpiece is often greater than the size of an ion beam, hybrid scan ion implanters are often employed to enable an ion beam to scan over a surface of a workpiece. Hybrid scan ion implanters rely upon a time varying electric or magnetic field to scan a beam (e.g., a pencil beam) back and forth over a scan path (e.g., into a ribbon beam), thereby effectively spreading out a beam, while moving a workpiece in an orthogonal direction. This hybrid scanning therefore allows an ion beam to be scanned over the entire surface of a workpiece.
In general, it is desirable to provide high wafer throughput by maximizing the beam current of an ion beam. To produce and transport an ion beam efficiently through a beam line it is desirable to have a beam comprising an overall charge neutrality (e.g., to form an ion beam plasma having a substantially equal density of both positively charged and negatively charged particles). Charge neutrality helps to prevent beam blow up (e.g., the tendency of the like charged ions comprising a beam to repel each other, thereby causing the beam to diverge away from its intended path), which can cause beam loss.
In general, it is also desirable to provide uniform implantation of the workpiece. Beam blowup, occurring differently along different paths through the beam line, may cause a change of ion beam properties, such as current or size, across the scan path. If these non-uniformities are not corrected the workpiece may be implanted non-uniformly and wafer yield (i.e. the ratio of wafer area implanted with desired properties to total wafer area) may suffer.